A pillar is a semiconductor chip-to-package interconnect technology. The advantages in the pillars lie in the extendibility to finer pitch and the superior electromigration (EM) performance compared to conventional solder C4's (controlled collapse chip connection). The pillar may be made from copper and provides the enhanced EM performance but increases the die stress for chip-to-chip and chip-to-wafer joints (i.e., 3D applications). The finer pitch is due to its vertical sidewall.
In copper pillar technology, a small amount of solder is still required to connect the copper pillars on the chips to the pad on the substrate. Sometimes the solder may wet the sidewall of the pillar. In some applications pillar sidewall wetting may be beneficial. For example, in implementations where solder is attached a receiving pad of a substrate or carrier, the pillar may include wettable sidewalls to ensure adequate electrical connection between the chip and package. However, in other applications sidewall wetting is undesired. For example, referring to FIG. 1A and FIG. 1B a conventional copper pillar structure with wettable sidewall is shown. Here, the solder will flow onto the sidewall of the copper pillars. This can cause bridging between adjacent pillars which, in turn, results in shorting (see, FIG. 1B). Also, although the pillars can be used in finer pitch applications, the solder wetting may require the pillars to be placed farther apart than desired. For this reason, it is not possible to provide a denser structure of connections.